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Overview
Features and Benefits
- High performance
- Throughput: 2 MSPS per channel maximum
- INL: ±0.9 ppm maximum from −40°C to +125°C
- SNR: 105.7 dB typical
- THD: −127 dB typical
- NSD: −166 dBFS/Hz typical
- Low power
- 15 mW per channel at 2 MSPS
- 1.5 mW per channel at 10 kSPS
- Easy Drive features reduce system complexity
- Very low 0.6 μA input current for dc inputs
- Wide input common-mode range: −(1/128) × VREF to +(129/128) × VREF
- Flexible external reference voltage range: 4.096 V to 5 V
- Accurate integrated reference buffer with 2 μF bypass capacitor
- Programmable block averaging filter with up to 216 decimation
- Extended sample resolution to 30 bits
- Over range and synchronization bits
- Flexi-SPI digital interface
- 1, 2, or 4 SDO lanes/channel allows slower SCK
- Echo clock mode simplifies use of digital isolator
- Compatible with 1.2 V to 1.8 V logic
- 7 mm × 7 mm 64-Ball CSP_BGA package with internal supply and reference capacitors to help reduce system footprint
Product Details
The AD4630-24 is a two-channel, simultaneous sampling, Easy Drive, 2 MSPS successive approximation register (SAR) analog-to-digital converter (ADC). With a guaranteed maximum ±0.9 ppm INL and no missing codes at 24-bits, the AD4630-24 achieves unparalleled precision from −40°C to +125°C. Figure 1 in the data sheet shows the functional architecture of the AD4630-24.
A low-drift, internal precision reference buffer eases voltage reference sharing with other system circuitry. The AD4630-24 offers a typical dynamic range of 106 dB when using a 5 V reference. The low noise floor enables signal chains requiring less gain and lower power. A block averaging filter with programmable decimation ratio can increase dynamic range up to 153 dB. The wide differential input and common mode ranges allow inputs to use the full ±VREF range without saturating, simplifying signal conditioning requirements and system calibration. The improved settling of the Easy Drive analog inputs broadens the selection of analog front-end components compatible with the AD4630-24. Both single-ended and differential signals are supported.
The versatile Flexi-SPI serial interface eases host processor and ADC integration. A wide data clocking window, multiple SDO lanes, and optional dual data rate (DDR) data clocking can reduce the serial clock to 10 MHz while operating at a sample rate of 2 MSPS. Echo clock mode and ADC master clock mode relax the timing requirements and simplify the use of digital isolators.
The 64-ball chip scale package ball grid array (CSP_BGA) of the AD4630-24 integrates all critical power supply and reference bypass capacitors, reducing the footprint and system component count, and lessening sensitivity to board layout.
APPLICATIONS
- Automatic test equipment
- Digital control loops
- Medical instrumentation
- Seismology
- Semiconductor manufacturing
- Scientific instrumentation
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Recommended for New Designs
This product has been released to the market. The data sheet contains all final specifications and operating conditions. For new designs, ADI recommends utilization of these products.
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Tools & Simulations
LTspice
LTspice® is a powerful, fast and free simulation software, schematic capture and waveform viewer with enhancements and models for improving the simulation of analog circuits.
Models for the following parts are available in LTspice:
Precision ADC Driver Tool
The Precision ADC Driver Tool is a web application that simulates the performance of precision ADC and driver combinations. Potential issues with driver selection, kickback settling, and distortion are flagged, and design tradeoffs can be quickly evaluated. Simulations and calculations include system noise, distortion, and settling of the ADC input
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