Communications Test Equipment

The AD9361 is a high performance, highly integrated radio frequency (RF) Agile Transceiver™ designed for use in 3G and 4G base station applications. Its programmability and wideband capability make it ideal for a broad range of transceiver applications. The device combines a RF front end with a flexible mixed-signal baseband section and integrated frequency synthesizers, simplifying design-in by providing a configurable digital interface to a processor. The AD9361 receiver LO operates from 70 MHz to 6.0 GHz and the transmitter LO operates from 47 MHz to 6.0 GHz range, covering most licensed and unlicensed bands. Channel bandwidths from less than 200 kHz to 56 MHz are supported.

The two independent direct conversion receivers have state-of-the-art noise figure and linearity. Each receive (RX) subsystem includes independent automatic gain control (AGC), dc offset correction, quadrature correction, and digital filtering, thereby eliminating the need for these functions in the digital baseband. The AD9361 also has flexible manual gain modes that can be externally controlled. Two high dynamic range analog-to-digital converters (ADCs) per channel digitize the received I and Q signals and pass them through configurable decimation filters and 128-tap finite impulse response (FIR) filters to produce a 12-bit output signal at the appropriate sample rate.

The transmitters use a direct conversion architecture that achieves high modulation accuracy with ultralow noise. This transmitter design produces a best in class TX error vector magnitude (EVM) of <−40 dB, allowing significant system margin for the external power amplifier (PA) selection. The on-board transmit (TX) power monitor can be used as a power detector, enabling highly accurate TX power measurements.

The fully integrated phase-locked loops (PLLs) provide low power fractional-N frequency synthesis for all receive and transmit channels. Channel isolation, demanded by frequency division duplex (FDD) systems, is integrated into the design. All VCO and loop filter components are integrated. The core of the AD9361 can be powered directly from a 1.3 V regulator. The IC is controlled via a standard 4-wire serial port and four real-time input/output control pins. Comprehensive power-down modes are included to minimize power consumption during normal use. The AD9361 is packaged in a 10 mm × 10 mm, 144-ball chip scale package ball grid array (CSP_BGA).

Applications

• Point to point communication systems
• Femtocell/picocell/microcell base stations
• General-purpose radio systems

The AD9371 is a highly integrated, wideband RF transceiver offering dual channel transmitters and receivers, integrated synthesizers, and digital signal processing functions. The IC delivers a versatile combination of high performance and low power consumption required by 3G/4G micro and macro BTS equipment in both FDD and TDD applications. The AD9371 operates from 300 MHz to 6000 MHz, covering most of the licensed and unlicensed cellular bands. The IC supports receiver bandwidths up to 100 MHz. It also supports observation receiver and transmit synthesis bandwidths up to 250 MHz to accommodate digital correction algorithms.

The transceiver consists of wideband direct conversion signal paths with state-of-the-art noise figure and linearity. Each complete receiver and transmitter subsystem includes dc offset correction, quadrature error correction (QEC), and programmable digital filters, eliminating the need for these functions in the digital baseband. Several auxiliary functions such as an auxiliary analog- to-digital converter (ADC), auxiliary digital-to-analog converters (DACs), and general-purpose input/outputs (GPIOs) are integrated to provide additional monitoring and control capability.

An observation receiver channel with two inputs is included to monitor each transmitter output and implement interference mitigation and calibration applications. This channel also connects to three sniffer receiver inputs that can monitor radio activity in different bands.

The high speed JESD204B interface supports lane rates up to 6144 Mbps. Four lanes are dedicated to the transmitters and four lanes are dedicated to the receiver and observation receiver channels.

The fully integrated phase-locked loops (PLLs) provide high performance, low power fractional-N frequency synthesis for the transmitter, the receiver, the observation receiver, and the clock sections. Careful design and layout techniques provide the isolation demanded in high performance base station applications. All voltage controlled oscillator (VCO) and loop filter components are integrated to minimize the external component count.

A 1.3 V supply is required to power the core of the AD9371, and a standard 4-wire serial port controls it. Other voltage supplies provide proper digital interface levels and optimize transmitter and auxiliary converter performance. The AD9371 is packaged in a 12 mm × 12 mm, 196-ball chip scale ball grid array (CSP_BGA).

Applications

• 3G/4G micro and macro base stations (BTS)
• 3G/4G multicarrier picocells 
• FDD and TDD active antenna systems 
• Microwave, nonline of sight (NLOS) backhaul systems

The AD9164¹ is a high performance, 16-bit digital-to-analog converter (DAC) and direct digital synthesizer (DDS) that supports update rates to 6 GSPS. The DAC core is based on a quad-switch architecture coupled with a 2× interpolator filter that enables an effective DAC update rate of up to 12 GSPS in some modes. The high dynamic range and bandwidth makes these DACs ideally suited for the most demanding high speed radio frequency (RF) DAC applications.

The DDS consists of a bank of 32, 32-bit numerically controlled oscillators (NCOs), each with its own phase accumulator.

When combined with a 100 MHz serial peripheral interface (SPI) and fast hop modes, phase coherent fast frequency hopping (FFH) is enabled, with several modes to support multiple applications.

In baseband mode, wide analog bandwidth capability combines with high dynamic range to support DOCSIS 3.1 cable infrastructure compliance from the minimum of one carrier up to the full maximum spectrum of 1.791 GHz of signal bandwidth. A 2× interpolator filter (FIR85) enables the AD9164 to be configured for lower data rates and converter clocking to reduce the overall system power and ease the filtering requirements. In Mix-Mode^™ operation, the AD9164 can reconstruct RF carriers in the second and third Nyquist zones up to 7.5 GHz while still maintaining exceptional dynamic range. The output current can be programmed from 8 mA to 38.76 mA. The AD9164 data interface consists of up to eight JESD204B serializer/deserializer (SERDES) lanes that are programmable in terms of lane speed and number of lanes to enable application flexibility.

An SPI interface configures the AD9164 and monitors the status of all registers. The AD9164 is offered in a 165-ball, 8 mm × 8 mm, 0.5 mm pitch CSP_BGA package, and a 169-ball, 11 mm × 11 mm, 0.8 mm pitch, CSP_BGA package, including a leaded ball option.

Product Highlights

1. High dynamic range and signal reconstruction bandwidth supports RF signal synthesis of up to 7.5 GHz.
2. Up to eight lanes JESD204B SERDES interface flexible in terms of number of lanes and lane speed.
3. Bandwidth and dynamic range to meet DOCSIS 3.1 compliance and multiband wireless communications standards with margin. 

Applications

• Broadband communications systems
  
  • DOCSIS 3.1 CMTS/ video on demand (VOD)/edge quadrature amplitude modulation (EQAM)
• Wireless communications infrastructure
  
  • W-CDMA, LTE, LTE-A, point to point

The AD9172 is a high performance, dual, 16-bit digital-to-analog converter (DAC) that supports DAC sample rates to 12.6 GSPS. The device features an 8-lane, 15 Gbps JESD204B data input port, a high performance, on-chip DAC clock multiplier, and digital signal processing capabilities targeted at single-band and multiband direct to radio frequency (RF) wireless applications.

The AD9172 features three complex data input channels per RF DAC that are bypassable. Each data input channel includes a configurable gain stage, an interpolation filter, and a channel numerically controlled oscillator (NCO) for flexible, multiband frequency planning. The device supports up to a 1.5 GSPS complex data rate per input channel and is capable of aggregating multiple complex input data streams up to a maximum complex data rate of 1.5 GSPS. Additionally, the AD9172 supports ultrawide bandwidth modes bypassing the channelizers to provide maximum data rates of up to 3.08 GSPS (with 16-bit resolution) and 4.1 GSPS (with 12-bit resolution).

The AD9172 is available in a 144-ball BGA_ED package.

Product Highlights

1. Supports single-band and multiband wireless applications with three bypassable complex data input channels per RF DAC at a maximum complex input data rate of 1.5 GSPS. One independent NCO per input channel.
2. Ultrawide bandwidth channel bypass modes supporting up to 3 GSPS data rates with 16-bit resolution and 4 GSPS with 12-bit resolution.
3. Low power dual converter decreases the amount of power consumption needed in high bandwidth and multichannel applications.

Applications

• Wireless communications infrastructure
  • Multiband base station radios
  • Microwave/E-band backhaul systems
• Instrumentation, automatic test equipment (ATE)
• Radars and jammers

The AD9208 is a dual, 14-bit, 3 GSPS analog-to-digital converter (ADC). The device has an on-chip buffer and a sample-and- hold circuit designed for low power, small size, and ease of use. This product is designed to support communications applications capable of direct sampling wide bandwidth analog signals of up to 5 GHz. The −3 dB bandwidth of the ADC input is 9 GHz. The AD9208 is optimized for wide input bandwidth, high sampling rate, excellent linearity, and low power in a small package.

The dual ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. The analog input and clock signals are differential inputs. The ADC data outputs are internally connected to four digital downconverters (DDCs) through a crossbar mux. Each DDC consists of up to five cascaded signal processing stages: a 48-bit frequency translator (numerically controlled oscillator (NCO)), and up to four half-band decimation filters. The NCO has the option to select preset bands over the general-purpose input/output (GPIO) pins, which enables the selection of up to three bands. Operation of the AD9208 between the DDC modes is selectable via SPI-programmable profiles.

In addition to the DDC blocks, the AD9208 has several functions that simplify the automatic gain control (AGC) function in a communications receiver. The programmable threshold detector allows monitoring of the incoming signal power using the fast detect control bits in Register 0x0245 of the ADC. If the input signal level exceeds the programmable threshold, the fast detect indicator goes high. Because this threshold indicator has low latency, the user can quickly turn down the system gain to avoid an overrange condition at the ADC input. In addition to the fast detect outputs, the AD9208 also offers signal monitoring capability. The signal monitoring block provides additional information about the signal being digitized by the ADC.

The user can configure the Subclasss 1 JESD204B-based high speed serialized output in a variety of one-lane, two-lane, four- lane, and eight-lane configurations, depending on the DDC configuration and the acceptable lane rate of the receiving logic device. Multidevice synchronization is supported through the SYSREF± and SYNCINB± input pins.

The AD9208 has flexible power-down options that allow significant power savings when desired. All of these features can be programmed using a 3-wire serial port interface (SPI).

The AD9208 is available in a Pb-free, 196-ball BGA, specified over the −40°C to +85°C ambient temperature range. This product is protected by a U.S. patent.

Note that throughout this data sheet, multifunction pins, such as FD_A/GPIO_A0, are referred to either by the entire pin name or by a single function of the pin, for example, FD_A, when only that function is relevant.

1. Wide, input −3 dB bandwidth of 9 GHz supports direct radio frequency (RF) sampling of signals up to about 5 GHz.
2. Four integrated, wideband decimation filter and NCO blocks supporting multiband receivers.
3. Fast NCO switching enabled through GPIO pins.
4. A SPI controls various product features and functions to meet specific system requirements.
5. Programmable fast overrange detection and signal monitoring.
6. On-chip temperature dioide for system thermal management.
7. 12mm × 12mm 196-Lead BGA

Applications

• Diversity multiband, multimode digital receivers
• 3G/4G, TD-SCDMA, W-CDMA, GSM, LTE, LTE-A
• Electronic test and measurement systems
• Phased array radar and electronic warfare
• DOCSIS 3.0 CMTS upstream receive paths
• HFC digital reverse path receivers

The ADL5380 is a broadband quadrature I-Q demodulator that covers an RF/IF input frequency range from 400 MHz to 6 GHz. With a NF = 10.9 dB, IP1dB = 11.6 dBm, and IIP3 = 29.7 dBm @ 900 MHz, the ADL5380 demodulator offers outstanding dynamic range suitable for the demanding infrastructure direct-conversion requirements. The differential RF inputs provide a well-behaved broadband input impedance of 50 Ω and are best driven from a 1:1 balun for optimum performance.

Excellent demodulation accuracy is achieved with amplitude and phase balances of ~0.07 dB and ~0.2°, respectively. The demodulated in-phase (I) and quadrature (Q) differential outputs are fully buffered and provide a voltage conversion gain of ~7 dB. The buffered baseband outputs are capable of driving a 2 V p-p differential signal into 200 Ω.

The fully balanced design minimizes effects from second-order distortion. The leakage from the LO port to the RF port is <−50 dBm. Differential dc offsets at the I and Q outputs are typically <20 mV. Both of these factors contribute to the excellent IIP2 specification, which is >65 dBm.

The ADL5380 operates off a single 4.75 V to 5.25 V supply. The supply current is adjustable by placing an external resistor from the ADJ pin to either the positive supply, VS, (to increase supply current and improve IIP3) or to ground (which decreases supply current at the expense of IIP3).

The ADL5380 is fabricated using the Analog Devices, Inc., advanced silicon-germanium bipolar process and is available in a 24-lead exposed paddle LFCSP.

Applications

The ADL5375 is a broadband quadrature modulator designed for operation from 400 MHz to 6 GHz. Its excellent phase accuracy and amplitude balance enable high performance intermediate frequency or direct radio frequency modulation for communication systems.

The ADL5375 features a broad baseband bandwidth, along with an output gain flatness that varies no more than 1 dB from 450 MHz to 3.8 GHz. These features, coupled with a broadband output return loss of <−14 dB, make the ADL5375 ideally suited for broadband zero IF or low IF-to-RF applications, broadband digital predistortion transmitters, and multiband radio designs.

The ADL5375 accepts two differential baseband inputs and a single-ended LO. It generates a single-ended 50 Ω output. The two versions offer input baseband bias levels of 500 mV (ADL5375-05) and 1500 mV (ADL5375-15).

The ADL5375 is fabricated using an advanced silicon-germanium bipolar process. It is available in a 24-lead, exposed paddle, Pb-free, LFCSP_VQ package. Performance is specified over a −40°C to +85°C temperature range. A Pb-free evaluation board is also available.

Applications

• Cellular communication systems
  GSM/EDGE, CDMA2000, W-CDMA, TD-SCDMA
• WiMAX/broadband wireless access systems
• Satellite modems

The ADF5356 allows implementation of fractional-N or integer N phase-locked loop (PLL) frequency synthesizers when used with an external loop filter and an external reference frequency. The wideband microwave VCO design permits frequency operation from 6.8 GHz to 13.6 GHz at one radio frequency (RF) output. A series of frequency dividers at another frequency output permits operation from 53.125 MHz to 6800 MHz.

The ADF5356 has an integrated VCO with a fundamental output frequency ranging from 3400 MHz to 6800 MHz. In addition, the VCO frequency is connected to divide by 1, 2, 4, 8, 16, 32, or 64 circuits that allow the user to generate RF output frequencies as low as 53.125 MHz. For applications that require isolation, the RF output stage can be muted. The mute function is both pin- and software-controllable.

Control of all on-chip registers is through a simple 3-wire interface. The ADF5356 operates with analog and digital power supplies ranging from 3.15 V to 3.45 V, with charge pump and VCO supplies from 4.75 V to 5.25 V. The ADF5356 also contains hardware and software power-down modes.

Applications

• Wireless infrastructure (LTE, W-CDMA, TD-SCDMA, WiMAX, GSM, PCS, DCS)
• Point to point and point to multipoint microwave links
• Satellites and very small aperture terminals (VSATs)
• Test equipment and instrumentation
• Clock generation